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najaeda/naja-scope

by najaeda

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Lets AI agents explore elaborated SystemVerilog/Verilog designs (RTL or gate-level netlists) without pasting RTL into context: trace signal fan-in/fan-out, walk module hierarchy, and jump to exact file:line source, backed by the najaeda netlist engine.

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scraper-ingested
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0 views15 on GitHub(as of 8/16/2026)
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Lets AI agents explore elaborated SystemVerilog/Verilog designs (RTL or gate-level netlists) without pasting RTL into context: trace signal fan-in/fan-out, walk module hierarchy, and jump to exact file:line source, backed by the najaeda netlist engine.

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